1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and in particular, to a mask control technique for the synchronous semiconductor memory device to receive an external signal such as a mask signal in synchronization with a system clock signal externally supplied in a periodic manner, to perform input/output of data at rising and falling edges of the system clock signal and to output a strobe signal to the outside. More specifically, the present invention relates to a random-accessible synchronous dynamic random access memory (SDRAM) and a technique preferably adapted to a mask control for a memory module.
2. Description of the Background Art
Though an operating speed of a dynamic RAM (DRAM) used as a main memory has been improved, yet it can not catch up with that of a microprocessor (MPU). Therefore, it is often said that the slow access time and cycle time of the DRAM should be a bottleneck in improving performance of an entire system. Then, recently, an SDRAM which operates in synchronization with an external system clock signal has been proposed as a main memory for a high-speed MPU.
To realize a high-speed access in an SDRAM, proposed is continuous access in synchronization with the system clock signal, e.g., fast access to a continuous sequence of eight bits of data by a data input/output terminal. Standard timing charts which meet the specification of this continuous access are shown in FIGS. 25A to 25F and 26A to 26F.
These figures show an operation of an SDRAM for input/output of 8-bit data (i.e., 1-byte data) by each of eight data input/output terminals. The SDRAM continuously reads/writes 8-bit data (8.times.8=64 bits in total). The number of bits to be continuously read is termed a burst length. The burst length of an SDRAM can be changed by a mode register.
In the SDRAM of FIGS. 25A to 25F and 26A to 26F, external control signals (such as a row address strobe signal /RAS, a column address strobe signal /CAS, an address signal Add., a write enable signal /WE) are inputted to a memory chip at a rising edge of an external clock signal ext.CLK which is a system clock.
The address signal Add. consists of time-division multiplexed row address signal X and column address signal Y. When the row address strobe signal /RAS is in active state of "L" level at a rising edge of the external clock signal ext.CLK, the address signal Add. is inputted as a row address signal Xa.
When the column address strobe signal /CAS is in active state of "L" level at a rising edge of the external clock signal ext.CLK, the address signal Add. is inputted as a column address signal Yb. In accordance with the inputted row address signal Xa and column address signal Yb, selection of row and column in a chip of the SDRAM is performed.
The first one of the 8-bit data D/Q is outputted when a predetermined clock period (three clock cycles in FIG. 25F) after the column address strobe signal /CAS falls to "L" level. The number of clocks from the fall of the column address strobe signal /CAS into "L" to the beginning of output of the data D/Q is called "CAS latency", and the CAS latency is determined by the mode register like the burst length. After that, the data q1 to q7 are sequentially outputted in response to a rise of the clock signal ext.CLK.
In writing data, the row address signal Xc is inputted like in reading data. When the column address strobe signal /CAS and the write enable signal /WE are in active state of "L" level at a rising edge of the external clock signal ext.CLK, a column address signal Yd is inputted and data d0 which has been given is inputted to be written. In response to the fall of the external control signals /RAS and /CAS, selection of row and column in the SDRAM is performed. After that, the data d1 to d7 are sequentially written into memory cells in synchronization with the clock signal ext.CLK.
Thus, unlike a conventional DRAM which receives an address signal and input data in synchronization with the external control signals, such as the row address strobe signal /RAS and the column address strobe signal /CAS, an SDRAM receives the external control signals, such as the address strobe signals /RAS and /CAS, the address signal Add. and the write enable signal /WE, and the input data D/Q at a rising edge of the external system clock signal ext.CLK.
Inputting the external control signals and data and reading the data in synchronization with the external clock signal has an advantage of eliminating the need for providing a margin for data input/output time to accommodate a skew (time lag) of the address signal, resulting in less cycle time, and so on. This synchronous operation will allow a high-speed continuous access.
An exemplary system using such an SDRAM is schematically shown in the block diagram of FIG. 27. The system includes a clock generator 2P for generating the system clock signal ext.CLK, a memory controller 3P and an SDRAM device (memory) 1P. The memory controller 3P and the memory 1P perform data transfer using the system clock signal ext. CLK as a trigger. In FIG. 27, the above external control signals and data are generally represented by reference sign 4P.
The SDRAM of FIGS. 25A to 25F, 26A to 26F and 27 has a problem of time lag of signal transfer among modules or among elements which becomes appreciable as the operating frequency becomes faster. For example, when access is made to memory chips in modules by the memory controller 3P, time differential in arrivals of the system clock signal ext.CLK to the memory chips and time differential in arrivals of data from the memory chips to the memory controller 3P are totally recognized as a skew at the time when the memory controller 3P receives data.
To reduce the skew, proposed is a configuration in which a function that each memory chip outputs a strobe signal QSP serving as a trigger signal concurrently with the output of data to the memory controller is added to the above SDRAM. A system using such an SDRAM is shown in FIG. 28, and an exemplary operation timing of each memory chip in the SDRAM is shown in FIGS. 29A to 29E.
The exemplary system operation of FIGS. 29A to 29E has an operation for masking data output in reading data, i.e., a control operation of data masking. The SDRAM performs a data transfer at the rising and falling edges of the system clock signal ext.CLK, unlike that of FIG. 27. In FIGS. 29C and 29E, reference signs DQM and QSF represent a data mask signal and a strobe signal, respectively.
An internal configuration of the SDRAM device 1P of FIG. 28 is shown in FIG. 30. An operation timing of each of memory chips MCP1 to MCPn of FIG. 30 is shown in FIGS. 29A to 29E.
The strobe signal QSP is activated in advance of outputting the data DQ and brought into intermediate potential Hi-Z again when the output of the data DQ is terminated. Therefore, the strobe signal QSP is brought back into the intermediate potential Hi-Z also when the memory controller 3P (FIG. 28) supplies the data mask signal DQM to achieve data masking, as shown in FIGS. 29A to 29B.
As discussed above, the above configuration of an SDRAM, in which each memory chip outputs a strobe signal for trigger along with data and stops outputting the strobe signal if it is intended to terminate outputting data by masking, resolves the problem of skew and allows the external memory controller to clearly recognize which memory chip outputs the transferred data.
In the SDRAM of FIGS. 28, 29A to 29E and 30, however, there arises a new problem of increased interconnection on the modules since the memory chips on the same module each output a strobe signal QSP and data DQ together.